1. Field of the Invention
The invention pertains to the modeling and estimating of substrate characteristics in preferably multi-layer chip carrier designs. More particularly, the invention is directed to physical modeling of electronic modules, including the interconnection of chip and chip carriers, such as the count calculation of chip carrier layers in order to optimize chip carrier designs by employing surface laminar circuitry (SLC) or buildup technology; and quantifies the number of redistribution layers of the chip carriers.
2. Discussion of the Prior Art
In essence, several methods are available in the technology for modeling chip and chip carrier interconnection layouts.
One approach is to review a data base of all previously designed modules, and select the one with matching fundamental parameters, such as die size, carrier size, and the number of chip inputs/outputs. However, a problem existent with this approach resides in the difficulty of identifying and dealing with all of the above-mentioned parameters which are required to attain the intended goals. Another approach is to build the design from the start; this being a time consuming process that often results in the necessity for discarding the design as the parameters change due to new requirements and/or design objectives.
A further approach would be to initially prepare a layout or sketch of the die showing the die pad positions required by a customer and then to laminate manually. The problem with this approach again resides in the level of skill and experience required in effecting the foregoing, and the difficulty in identifying and dealing with all of the parameters required, and the difficulty in visually expressing and modifying the design as may be necessary in order to meet all conditions.
There is, consequently, a need in the technology for a method and system providing for a quick and visual representation of a complicated module design which takes into account all relevant parameters. This is needed for early modeling of a more complex process and essentially useful for the early design and quick modeling of chip carriers, such as plastic ball grid array (PBGA), flip chip, or wirebond chip carriers.
As disclosed in the parent application, Ser. No. 09/429,990, an object is to provide an improved system and method for simulating and graphically assessing the cost and feasibility of general and specific wiring design cases. Another purpose is to provide a system and method for simulating general and specific wiring design cases and quickly assess the simulated design graphically. Moreover, provision is made for a system and method for assessing a simulated wiring design with respect to crossing, choking, signal runs, wiring channels and input/output; and for transmitting simulated design graphical data to a wiring design tool.
In accordance with the foregoing, pursuant to the disclosure of the parent application, a system and method is provided for modeling and estimating substrate characteristics preliminary to preparing a detailed design. Input parameters include die size and substrate size and, optionally, a netlist of interconnections between the die and substrate. Responsive to these input parameters, a representation of an optimized estimated fanout of the interconnections is graphically presented together with a set of substrate parameters derived from the optimized estimated fanout. In that connection, a computer program product is configured to be operable to graphically model an optimized fanout of die to substrate interconnections.
In essence, as a further improvement over the parent application, which relates to a chip carrier design simulation, estimator, and an early design for providing a system for quickly modeling and estimating substrate characteristic including optimized single layer fanout, substrate parameters such as size, wiring rules and I/O layout, the present invention provides a tool which is a system or method for electrically estimating multilayer substrates for various chip carrier designs as set forth herein.
Basically, the problem which is solved by the present invention with regard to a chip carrier layer count calculation resides in that an accurate and fast estimate for various customer die designs is provided in that the customer provides a die showing die pad position, and a further request as to the physical size of the package, the package I/O, the design rules, the number of layers and ultimately the cost.
For that purpose, the inventive concept is grounded in providing a subroutine as part of the overall program generally referred to as buildup technology or SLC (surface laminar circuitry). Thus, given the specified input parameters, the invention provides a program determinative of the number of signal distribution layers required to access module I/O bumps (BGA""s).